For wireless communication systems, local oscillator signals for frequency translation of received and/or transmitted signals are generated by phase-locked loop (PLL) frequency synthesizers. PLLs are also widely used in other electronic systems. For example, PLLs may be used as clock generators for high performance microprocessors.
Key performance parameters of a PLL include phase noise, spurious response, lock time, cost and power consumption. The spurious tones can degrade performance for both transmitters and receivers. For transmitters using a local oscillator signal having high spurious tones, the transmitted signal can cause excessive emission power in adjacent channels. For receivers, the spurious tones of a local oscillator signal down-convert undesired noises to baseband. Thus, system noise performance can be degraded. For high performance wireless cellular communication systems, low phase noise and low spurious tones are typically required to improve receiver sensitivity performance and to reduce the effects of blocking signals.
For PLL frequency synthesizers, spurious tones might occur in the output spectrum for several reasons. First, non-ideal performance of analog circuitry, such as charge pump delay and amplitude mismatch, leakage current, oscillator gain non-linearity and the like, causes limit cycle during steady-state. Second, fractional-N dividers, which are used in some cases to improve phase noise, can introduce phase disturbance to the PLL and result in spurious tones.
One technique to reduce spurious tones is based upon sampling the output of a small on-chip integration capacitor, which averages out the phase error. However, the conventional sampling technique suffers from saturation effect, which degrades system transient performance and requires a complex anti-saturation circuit to achieve a lock.
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